Digital control systems for electronic power devices that drive electric motors are limited to the generation of an input signal, particularly of the PWM type. The input signals are conveniently modulated by digital peripherals integrated in microcontrollers connected to the motors to be driven. However, the output of these digital peripherals cannot be directly connected to the electrical power devices, such as IGBT transistors, for example.
FIG. 1 schematically shows a driving stage 1 whose input is connected to a digital peripheral and whose output is connected to the motor. The driving stage 1 essentially comprises an inverting stage 2 and a power branch 3. The power branch comprises a first power element T1 and a second power element T2 in series to each other between a first voltage reference and a second voltage reference. The first voltage reference may be a supply voltage Vcc, and the second voltage reference may be ground GND. The first and second power elements T1, T2 may be IGBT transistors, for example.
The driving stage 1 has an input terminal IN1 coupled with the inverting stage 2, and receives a trigger signal PWM. The driving stage 1 has an output terminal OUT1 coinciding with the interconnection point of the first and second power elements T1, T2.
The first power element T1 is inserted between the supply voltage reference Vcc and the output terminal OUT1, and has a control terminal (gate) G1 connected to the input terminal IN1 of the driving stage 1 via the inverting stage 2. The first power element T1 is generally indicated as a high-side driver transistor. The second power element T2 is inserted between the output terminal OUT1 and the ground reference GND, and has a control terminal (gate) G2 directly connected to the input terminal IN1 of the driving stage 1. The second power element T2 is generally indicated as a low-side driver transistor.
When using this type of driving stage during the PWM signal switching, it must be ensured that short-circuits between the high-side and low-side power elements T1, T2 of the power branch 3 are not triggered. For this purpose, a convenient analog interface may be used for generating a delay of the PWM signal applied to the control terminals of power elements T1 and T2. In particular, the analog interface is traditionally mounted on the board and comprises the driving stage 1.
One approach is to manufacture an analog interface 4 for generating a desired delay as shown in FIG. 2. The analog interface 4 is inserted between the input terminal IN1 of the driving stage 1 and the control terminals G1, G2 of the first and second power elements T1, T2. In particular, the analog interface 4 comprises a first circuit branch 5 and a second circuit branch 6 connect in parallel to each other and inserted between the input terminal IN1 and the control terminals G1, G2 of the first and second power elements T1, T2.
The first circuit branch 5 comprises a first resistor R1 inserted in parallel with a first diode D1, both cascade connected to a first hysteresis block IST1. An interconnection point X1 between the first hysteresis block IST1 and parallel to the first resistor R1 and the first diode D1 is connected to ground GND by a first capacitor C1.
Similarly, the second circuit branch 6 comprises a second resistor R2 inserted in parallel with a second diode D2, both cascade connected to a second hysteresis block IST2. An interconnection point X2 between the second hysteresis block IST2 and parallel to the second resistor R2 and the second diode D2 is connected to ground GND by a second capacitor C2. Circuitry controlling the power element collector-emitter voltage VCE can also be used. Although advantageous under many aspects, these known approaches have a major drawback linked to the insertion of additional components on the board comprising the driving stage 1.